The present invention relates to an improved memory management method capable of efficient data transfer and a computer system and a tone generator system employing the memory management method.
Examples of the conventionally-known data transfer method for use in a computer system includes the so-called DMA (Direct Memory Access) method which is characterized by transferring data between a particular device and a main memory directly without intervention of a CPU (Central Processing Unit) of the system. Because the main memory is not managed via the CPU, the DMA method achieves data transfer at high speed.
In a so-called xe2x80x9cscatter/gatherxe2x80x9d DMA scheme, which is one example of the DMA method, a storage section of the main memory is divided into a plurality of small storage areas commonly called xe2x80x9cpagesxe2x80x9d so that the memory is managed on a page-by-page basis. Assuming that the main memory has a 32-Mbyte capacity and a virtual storage capacity is 4 Gbytes, each logical address can be expressed by 32 bits, each physical address by 25 bits and each address in each page by 12 bits. In such a case, the lower 12 bits in the logical address coincide with those of the physical address. However, because the individual pages are dispersed or scattered within the main memory, the 13th to 25th bits of the logical address do not necessarily coincide with the corresponding bits of the physical address. For this reason, it has been a common practice to transfer data after converting each logical address into a physical address using dedicated hardware.
When, for example, a predetermined quantity of data designated by consecutive logical addresses are to be transferred from the main memory to a particular device, the data within a certain page may be read out from the main memory using the lower 12 bits of the logical addresses by just identifying the location of that page in the main memory, because the data can be specified by the consecutive addresses. However, once the page is turned to another or next page, it is necessary to identify the other page. To this end, the conventional scheme generally employs dedicated hardware to detect each break between the pages. Upon detection of such a page break, the data transfer is suspended and an interrupt signal is generated, so that the following physical addresses can be acquired through an interrupt process routine executed by an operating system (abbreviated xe2x80x9cOSxe2x80x9d) and the data transfer is then resumed using the thus-acquired physical addresses.
In recent years, many computer systems are equipped with a so-called tone generator LSI incorporated therein for reproduction of recorded tones. In many cases, tone waveform data corresponding to various tone colors or timbres, such as those of piano and guitar, are prestored in the main memory so that desired tones are reproduced on the basis of the tone waveform data read out from the main memory. However, in cases where the tone waveform data are prestored in storage areas that are dispersedly provided within the main memory, a great number of interrupts would occur in accessing the tone waveform data, undesirably lowering the data transfer efficiency. In particular, the frequent interrupt occurrence would present significant inconveniences in cases where a variety of tone colors, such as those of piano, guitar and drum, are sounded simultaneously. For example, if tones of 64 channels are to be generated simultaneously in such a situation where each page has a capacity of 4 Kbytes and the sampling frequency is 48 kHz, an interrupt occurs every 3 ms (=4 k/(48*64)), which would prevent a smooth data transfer.
In other cases where such a scatter/gather process is not performed, there arises a need to prestore all the tone waveform data in successive storage areas (i.e., storage areas with consecutive addresses). But, there is no guarantee that a large size of such successive storage areas can always be secured in the main memory. Further, in waveform replacement processes, such as a DLS (Download Sample) process, where a piano tone color, for example, is converted into a guitar tone color, it is necessary that tone waveform data designated by a higher-order application be read out from a hard disk and replaced with those already stored in the main memory. Even in ordinary waveform reproduction, there is no need to keep the tone waveform data stored in the main memory after termination of tone reproduction, so that the storage areas in the main memory are usually freed after the tone reproduction. Namely, because the storage areas for storing the tone waveform data are secured and then freed in these cases, the necessity of securing the successive storage areas is not very great; thus, taking up the large-size successive storage areas in the main memory would yield great adverse effects on other applications.
It is therefore an object of the present invention to provide a memory management method which permits efficient use of a main memory by securing successive storage areas and scattered storage areas in the main memory and appropriately using these areas in a selective manner, as well as a computer system and a tone generator system employing such a memory management method.
In order to accomplish the above-mentioned object, the present invention provides a memory management method for use in a computer system including a memory, which comprises: a managing step of dividing the memory into a first storage section secured as a succession of storage areas with consecutive addresses and a second storage section secured as scatterable storage areas corresponding to a plurality of pages each having consecutive addresses of a predetermined size, and thereby managing the first storage section and the second storage section separately from each other; and a deciding step of, in accordance with a characteristic of data to be stored, deciding which one of the first storage section and second storage section the data should be stored in, the data being stored in the one storage section.
For data readout from the first storage section, if at least information indicative of a single physical address corresponding to a start position of the first storage section is obtained, it is possible to identify all physical addresses corresponding to individual read addresses on the basis of the obtained physical address. For data readout from the second storage section, however, it is necessary to obtain information indicative of physical addresses corresponding to start positions of the individual pages. Thus, in reading out the data from the first storage section, it is only necessary to receive the single physical address at the beginning of the intended data readout; however, in reading out the data from the second storage section, its is necessary to, at each break between the pages (xe2x80x9cpage breakxe2x80x9d), receive the physical address for a succeeding one of the pages. Considering this, it is preferable that data having a relatively high frequency of use be stored in the first storage section and data having a relatively low frequency of use be stored in the second storage section. Thus, in reading out, from the memory, such data whose frequency of use is relatively high, the invention can significantly reduce the number or frequency of interrupt occurrences necessary for acquiring physical addresses and hence the loads on a central processing unit (CPU) of a computer used. Further, by storing less-frequently used data in the second storage section, the present invention can make efficient use of the limited memory space. As a result, the present invention achieves efficient memory management in a well-balanced manner.
According to another aspect of the present invention, there is provided a memory management method for use in a computer system including a memory, the memory management method which comprises: a managing step of dividing the memory into a first storage section secured as a succession of storage areas with consecutive addresses and a second storage section secured as scatterable storage areas corresponding to a plurality of pages each having consecutive addresses of a predetermined size, and thereby managing the first storage section and the second storage section separately from each other; a step of storing data to be stored in the memory in one of the first storage section and the second storage section; and a step of reading out the data stored in one of the first storage section and the second storage section, in accordance with management by the managing step.
Here, the managing step may manage storage information indicating which one of the first storage section and the second storage section the data are stored in, and logical and physical addresses of the data, and the step of reading may comprise: a first step of, when given data are to be read out from the memory and transferred to a particular device, determining on the basis of the storage information which one of the first storage section and the second storage section the given data are stored in; a second step of, when the given data to be transferred have been determined as stored in the first storage section, receiving, from the managing step, a physical address indicative of a start position of the first storage section to sequentially generate read addresses beginning with the physical address of the start position, and using the read addresses to read out the given data from the memory to thereby transfer the given data to the particular device; and a third step of, when the given data to be transferred have been determined as stored in the second storage section, receiving, from the managing step, a physical address indicative of a start position of each of the pages of the second storage section to sequentially generate read addresses, each in the form of a physical address, for each of the pages on the basis of the physical address received from the managing step, and using the read addresses to read out the given data from the memory to thereby transfer the given data to the particular device.
Further, the third step may include a step of sequentially generating logical read addresses, a step of detecting a break between the pages on the basis of the read addresses, and a step of, on the basis of a result of detection by the step of detecting, converting the logical read addresses into physical read addresses using the physical address indicative of a start position of each of the pages.
According to still another aspect of the present invention, there is provided a computer system which comprises: a memory; a processor that executes processes including: a managing process for dividing the memory into a first storage section secured as a succession of storage areas with consecutive addresses and a second storage section secured as scatterable storage areas corresponding to a plurality of pages each having consecutive addresses of a predetermined size, and thereby managing the first storage section and the second storage section separately from each other; a process for storing data in one of the first storage section and the second storage section; and a process for instructing that desired data be read out from the memory; and a memory access device that generates read addresses in accordance with a read instruction from the processor and uses the read addresses to access the memory for reading out the data therefrom.
In a preferred implementation, when the data to be read out from the memory are stored in the first storage section, the memory access device receives, from the processor, a physical address indicative of a start position of the first storage section to sequentially generate read addresses beginning with the physical address of the start position, and uses the read addresses to read out the data from the memory, and when the data to be read out from the memory are stored in the second storage section, the memory access device receives, from the processor, a physical address indicative of a start position of each of the pages of the second storage section to sequentially generate read addresses, each in the form of a physical address, for each of the pages on the basis of the physical address received from the processor, and uses the read addresses to read out the data from the memory.
Further, the memory access device may include: an address calculator that executes incremental read-address calculating operations, when the data to be read out from the memory are stored in the first storage section, the address calculator sequentially generating read addresses beginning with the physical address indicative of a start position of the first storage section, when the data to be read out from the memory are stored in the second storage section, the address calculator sequentially generating logical read address; a detector that when the data to be read out from the memory are stored in the second storage section, detects a break between the pages on the basis of the logical read addresses; and an address converter that, on the basis of a result of detection by the detector, converts the logical read addresses into physical read addresses using the physical address indicative of a start position of each of the pages.
The present invention may be implemented not only as a memory management method for use in a computer system but also as a computer system employing such a memory management method. The present invention may also be practiced as a recording medium storing a computer program for carrying out the memory management method. The data to be stored in the memory are, for example, tone waveform data, but the present invention may be applied to any other types of data than such waveform data.